محاضرات في معمارية وبرمحة و ربط (موائمة ) معاجات انتل

Historical Background
Mechanical Age
Electrical Age
Programming Languages
Evolution of Data/Memory capabilities of Microprocessors
Operational Speed
Architectural Evolution
Microprocessor based PC Architecture
Memory and I/O System
The Microprocessor
PC Architecture – Overview
Number Systems
Digits in each number system
Positional Notation
Decimal Number System
Binary Number Systems
Octal and HexadecimalRepresentations
Conversion to/from Decimal System
Integer Conversion Examples
Conversion of Real Numbers to decimal (using positionalnotation)
Conversion of Real Numbers from decimal (using multiplication)
Binary Coded Hexadecimal
Complements
Computer Data Formats
ASCII Data
BCD (Binary Coded Decimal) Data
Byte-Sized Data
Unsigned: Range 0 to 255
Signed: Range –128 to 127
Word-Sized Data
Defining Word Sized Data
Doubleword-Sized Data
Assembly definitions
Non-Standard Data Widths
Real Numbers (or floating point numbers)
IEEE 754 v10
Why Floating Point Numbers ?
Drawbacks of fixed-point notation
Floating Point (FP) Real Numbers
Single-Precision Format (10 ±38)
Double-Precision Format (10 ±308)
Real Numbers
Defining real numbers

μP and its Architecture
Discuss the programming architecture of Intel
Family (8086-80486, Pentium-P4)
Discuss μP registers and detail the flag register
Real mode memory access
Protected mode memory access
Program-invisible registers found in 80286-P4
Operation of memory paging system
Pentium Block diagram
8086 Archtecture
8086 Block Diagram
Typical μP based Motherboard
Internal Microprocessor Architecture
The Programming Model
Program Visible
Program Invisible
Register Sizes
The Programming Model
Multi-purpose Registers
EFLAGS Register
Real Mode
Real Mode Memory Addressing
Segments & Offsets
Default Segment & Offset Registers
Advantages of segment:offset
Protected Mode OS Essentials
How do a Process/program Excecute
Memory Resource Hierarchy
Basic Memory Management
Variable Sized Partitions
Implementing Memory on Harddisk
Virtual Memory
Paging and Virtual Memory
Page Table Design Alternatives
Multi-level Page Tables
Translation Lookaside Buffers (TLBs)
Protected Mode Memory Addressing
Protected Mode Addressing
Selectors & Descriptors
Access Rights Byte
Segment Registers in Protected Mode
Selection of a Descriptor
Program Invisible Registers
Memory Paging
Paging Registers
Linear Address Format
TLB – (translation look-aside buffer)
Page Directory and Page Table



Data Addressing Modes
Fields in an Assembly Instruction
Data Addressing Modes
Register Addressing
Immediate Addressing
Direct Data Addressing
Displacement Data Addressing
Direct/Displacement Addressing Example
Register Indirect Addressing
Base-plus-Index Addressing
Register Relative Addressing
Base Relative-plus-Index Addressing
Scaled-Index Addressing
Data Structures in Assembly
Program Memory – Addressing Modes
Direct Program Memory Addressing
Relative Program Memory Addressing
Indirect Program Memory Addressing
Stack Memory Addressing Modes



Introduction
Instruction Format
Instructions Format – Examples
Instruction Format – Special Addressing Mode
Instruction Format – 32-bit Addressing Modes
Segment MOV Instructions
PUSH/POP
Load Effective Address
LDS, LES, LFS, LGS and LSS
String Data transfers
Direction Flag
DI and SI registers
LODS Instruction
STOS Instruction
STOS with a REP
MOVS Instructions
INS Instruction
OUTS Instruction
Miscellaneous Data Tx Instructions
XCHG (Exchange) Instruction
XLAT (Translate) Instruction
IN and OUT
Miscellaneous Data Tx Instructions
MOVSX (move with sign extend) – in x386+
MOVZX (move with zero extend) – in x386+
BSWAP (byte swap; 1<–>4, 2<–>3) – in x486+
CMOV (conditional move) – in Pentium+
Segment Override Prefix
Assembler Directives
Processor Specific: .286, .286P… .586, .586P
Co-processor Specific: .287, .387
ASM Specific: .model, .startup, .exit
Data definition: DB, DW, DWord, DD, DQ, DT
Start definition: macro, proc, segment, stack, struc
End definition: endm, endp, ends, end
Classifiers: byte, word, ptr, near, far, equ, offset
Coding Classifiers: org, use16, use32
Directives – some examples



Addition – ADD Instruction
Addition – INC Instruction
Addition – ADC instruction
Subtraction Instructions
SUB instruction
DEC instruction
SBB (subtraction-with-borrow) instruction
SUB AX, DI
SBB BX, SI
Comparison Instructions
CMP
CMPXCHG: (Compare & Exchange)
CMPSCHG8B (in Pentium+)
Multiplication – (I)MUL Instruction
MUL: usigned multiplication
IMUL: Signed multiplication
Division – (I)DIV Instruction
IDIV: signed division
DIV: unsigned division
Division – Remainder Handling
Option I: Rounding
Option II: Fraction
BCD and ASCII Arithmetic
BCD Instructions
DAA (Decimal adjust after addition)
DAS (Decimal adjust after subtraction)
ASCII Arithmetic
AAA (ASCII adjust after addition)
AAS (ASCII adjust after subtraction)
AAD (ASCII adjust before division)
AAM (ASCII adjust after multiplication)
Basic Logic Instructions
AND
OR
XOR
TEST and BIT (BT, BTC, BTR, BTS)
NOT(1’s complement) and NEG(2’s complement)
Shift & Rotate
Shift Instructions
Rotate Instructions
String Comparisons
SCAS (String Scan Instruction)
Variations SCASB, SCASW, SCASD
CMPS (String Compare Instruction)
Variations CMPSB, CMPW, CMPSD



The JUMP Group
Unconditional JUMP
Jumps with Register Operands
Indirect Jumps using an Index
Conditional Jumps
Conditional Sets (x386+)
Unconditional Loops (LOOP):
uses a combination of DEC CX and JNZ conditional
Jump
Conditional Loops:
OOPE (LOOPZ)
LOOPNE (LOOPNZ)
Controlling the Program Flow
MASM control statements
.IF, .ELSE, .ELSEIF, .ENDIF
.REPEAT-.UNTIL
.WHILE-.ENDW
Procedures
procedure (or sub-routines)
CALL
RET
Calls with Register Operands
Calls with Indirect Memory Addresses
RET Instruction
RET immediate instruction
Introduction to Interrupts
exceptions
INT
INTO
INT 3
Interrupt Vectors
interrupt descriptor table
Interrupt Instructions
INTs
Operation (PUSHF followed by a FAR CALL)
IRET/IRETD
INT 3
INTO
External Interrupt Control
STI (Set Interrupt)
CLI (Clear Interrupt)
STI is typically the first instruction in any interrupt service routine
Machine Control & Misc. Instructions
Carry Flag Control
WAIT
HLT (Halt)
NOP (No operation)
LOCK Prefix
ESC (Escape)
BOUND (x186+)
ENTER & LEAVE (x186 +)
ENTER
LEAVE


Modular Programming
The Assembler
The Linker
Public & Extrn
PUBLIC
EXTRN
Libraries
Macros
Local Variables in a macro
Using the Keyboard & Video Display
3 ways to read the keyboard
Writing to the Video Display
The Mouse
Testing for a mouse
Verifying the mouse driver
Using a mouse
Data Conversions
Binary -> ASCII
ASCII -> Binary
Reading and displaying hexadecimal data
Using Look-up-Tables (LUTs) for data conversion
Disk Files
Disk Organization
File Names
Sequential File Access
File creation, reading, writing
File opening and closing
File Pointer
Random Access Files
Interrupt Hooks
Intercepting an Interrupt



Inline Assembly Language
Advantages
Restrictions
Issues
Inline Assembly Language – Examples
Assembly function via a Separate Assembly Module
Using Inline Assembly for functions
Mixing C/C++ with Assembly
Calling C Functions
Calling C++ Functions
Writing C-Macros in Assembly
C-Assembly for 32-bit Applications
Using OS Services via C
Using I/O Ports



Pin-outs and Pin Functions
Power Supply Requirements
Voltage
Power Supply Current
Operating Temperature
DC Characteristics
Input Characteristics
Output Characteristics
Recommended Logic Fan-out
Pin Connections
AD7-AD0
A15-A8
AD15-AD8
A19/S6 – A16/S3
!RD (Not Read)
READY
INTR
!TEST (Not Test)
NMI
RESET
CLK
Vcc
GND
MN/ !MX
!BHE / S7
Minimum & Maximum Mode
Minimum mode
Maximum mode
Minimum Mode Pins
IO/!M or M/!IO
!WR
!INTA
ALE
DT/!R
DEN
HOLD
HLDA
!SS0
Maximum Mode Pins
!S2, !S1, and !S0
!R1/!GT1 and
!R0/!GT0
!LOCK
QS1 and QS0
Clock Generator (8284)
Pin-out
8284A – Pin Description
!AEN1 and!AEN2
RDY1 and RDY2
!ASYNC
X1 and X2
F/!C
EFI
CLK
PCLK
OSC
!RES
RESET
CSYNC
GND
Vcc
8284A Operation
Clock generation:
8284A Clock Generator
An inverting buffer (output OSC)
2-to-1 MUX
The READY flipflop (READY synchronization).
The RESET flipflop
CLK
8284A Reset Operation
Bus Buffering and Latching
Computer systems have three buses:
Address
Data
Control
Fully Demultiplexed
Fully Buffered
Disadvantage
Timing delay
Bus Timing
Basic bus Operation
Timing in General
During T1
During T2
During T3
During T4
8086/88 Bus Timing Requirements
8086 Bus Timing Responses
Detailed Min Mode Read Operation
Detailed Min Mode Write Timing
Ready and the Wait State
Minimum Mode vs. Maximum Mode
Minimum Mode System
8288 – Bus Controller
Maximum Mode System



Memory Types
Two basic types:
ROM: Read-only memory
RAM: Read-Write memory
Four commonly used memories:
ROM
Flash (EEPROM)
Static RAM (SRAM)
Dynamic RAM (DRAM)
Generic pin configuration:
Memory Pin Connections
Address Pins
Data Pins
Selection Pins
Control Pins
Read-only Memory (ROM)
ROM
PROM
EPROM
Flash EEPROM
2716 EPROM
Timing Diagram
Selecting Modes of Operation
Static RAM
Timing
Read Cycle
Write Cycle 1
62256 (32K X RAM
Dynamic RAM (DRAM)
TI TMS 4464 DRAM
Row/Column Decoding
!CAS Operation
!RAS Operation
44256 DRAM
44256 DRAM Block Diagram
DRAMs are typically placed on SIMM (Single In-line Memory Modules) boards.
Typical Sizes
30-pin SIMMs come in 1M X 8, 1M X 9 (parity), 4M X 8, 4M X 9.
72-pin SIMMs come in 1/2/3/8/16M X 32 or 1M X 36 (parity)
The DIMM module is available in DRAM, EDO (extended data output), SDRAM and NVRAM with and without an EPROM
30 pin SIMM (4M x 9)
72 pin SIMM (4M x 36)
168 pin DIMM (16M x 64)
Address Decoding
Simple NAND Decoder
74LS138 – 3 to 8 Line Decoder
74LS139 – Dual 2 to 4 Line Decoder
Bipolar PROM Decoder
Programmable Logic Devices (PLDs)
AMD 16L8 PAL decoder.
PAL16L8 for eight 2764s
8088/188 Memory Interface
8088/188 (8-bit) EPROM Memory Interface
8088/188 (8-bit) RAM Memory Interface
8088/188 (8-bit) Flash Memory Interface
Parity for Memory Error Detection
74AS280 Parity Generator/Checker
Block-Check Character (BCC) or Checksum.
Cyclic Redundancy Check (CRC)
Error Correction
Hamming Codes
Error Correcting Hardware
74LS636 – Error Detection/Correction
80×86 (16-bit) Memory Interface
Memory Architecture
Dynamic RAM (revisited)
Dynamic RAM Controllers
PLD program for the DRAM Controller Schematics



Basic I/O Instructions
Isolated vs. Memory mapped I/O
PC I/O Map
Basic Input Interface
Basic Output Interface
Handshaking
Handshaking Mechanisms
Handshaking Example
Interfacing Circuitry
Interfacing Circuitry -Input Devices
Interfacing Circuitry – Output Devices
I/O Port Decoding
82C55 – Programmable Peripheral Interface
82C55 PPI – Pinouts
Interfacing the 82C55 PPI
Programming the 82C55
82C55 – Mode 0 Operation Example
82C55 – Mode 0 Operation
Mode 0 – LCD Interface
Mode 0 – Stepper Motor Interface
Flow Chart of a Keyboard Scanning Procedure
82C55 – Mode 1 Strobed Input
82C55 – Mode 1 Strobed Input Example
82C55 – Mode 1 Strobed Output
82C55 – Mode 2 Bi-directional Operation
8279 – Programmable Keyboard/Display Interface
8279 – Pinouts
8279 – Interface with 8088
8279 – Keyboard Interface
8279 – Interface
8279 – Six Digit Display Interface
8254 – Programmable Interval Timer
8254 – PIT Pinout
8254 Pin Function Definitions
8254 – Programming
8254 – Programming Modes
8254 – Waveform Generation
8254 – Counter Control & Status Registers
8254 – Motor Speed & Direction Control
16550 – Programmable Communications Interface
16550 – PCI/UART
16550 – PCI Pinout
16550 – PCI Programming
16550 – PCI Interface
16550 –Sending/Receiving data
Digital to Analog Converters (DACs)
DAC Interface
Analog to Digital Converters (ADCs)
ADC Interface
Microprocessor – Data Conversion Interface



Interrupts
Interrupt Vector Table
Real Mode Interrupts
Real and Protected Mode Interrupts
Interrupt Flag Bits
A Debug (Trace) Procedure
Storing an Interrupt Vector in Interrupt Table
Hardware Interrupts
Tri-state buffer for generating interrupt vector
Converting INTR into an edge-triggered request input
Example: 8255 Interrupt Configuration
Keyboard Interface
Handling more than 1 IRQ
Daisy Chained Mechanism
Multiple IRQs
8259A – Programmable Interrupt Controller
Connecting two 8259A – PICs
8259A – Programming
8259A – Interface with 16550 UART



80886/80188 vs. 8086/88
80186/88 – Different Versions
80186 Block Diagram
80186/88 – Features
80186 – Interrupt Control Unit
80186 – Timer/Counter Unit
80186 – DMA Control Unit
80186 – Chip Select Unit
80186 – Refresh Control Unit
80186 – Power Management
80186 – 80C187 Interface
80186 – ONCE Mode
Chip Select Unit
Chip Select Relative timings
Chip Select Unit
Programming
Programming /UCS
Programming /LCS
Programming /MCS
Programming /PCS
Programming /MCS & /PCS Alternate Control Registers
Typical 80186 System



Memory Writing
Memory Reading
Processor Timing Diagrams Minimum Mode System – Memory Interface
Important Processor Specifications
TAVDV – address access time
TAVDV = 3TCLCL – TCLAV – TDVCL
Address Access Time
from Address is Valid to Data is Valid
TRLDV – read access time
TRLDV = 2TCLCL – TCLRL – TDVCL
Read Access Time
from Read Signal is Low to Data is Valid
TDVWH – memory setup time
TDVWH = 2TCLCL – TCLDV +TCVCTX
Memory Setup Time
from Data is Valid to Write Signal is High
TWHDX – data hold time
TWHDX = TCLCH – X
Data Hold Time (after WR’)
from Write Signal is High to Data is Invalid (Inactive)
TWLWH – write pulse witdth
TWLWH = 2TCLCL – Y
Write Pulse Width / Write-Time
from Write Signal is Low to Write Signal is High
8088/86 Min Mode – Timing Specs
Timing requirements – 4 MHZ System
HM6264B – Timing Requirements
HM6264B – Read Timing Diagram
HM6264B – Write Timing Diagram
Compatible Timing Specs for HM6264B-8L
Comparing Timing Requirements of 8088 (using 4 MHz clock) and HM6264B-8L
M2764A Read Mode AC Characteristics
M2764A Read Mode Timing Diagram
Compatible Timing Specs for M2764A
What if we need to interface a “slow” memory to the 8088?
Comparing Timing Requirements of
8088 (using 4 MHz clock) and a certain “slow” memory chip
Write Pulse Width / Write-Time (TWLWH) with zero WS
Write Pulse Width / Write-Time (TWLWH) with 1 wait state
How do we produce a wait state
Requirements for the READY input of the 8088
Requirements for the RDY of the 8284
Bus Contention
I/O Port Contention
Contention in Dual-Port RAMs